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integrated silicon solution, inc. www.issi.com 1 rev. e 11/10/08 is24c01b is24c02b is24c01b/02b 2-wire (i 2 c) 1k-bit/2k-bit serial eeprom
2 integrated silicon solution, inc. www.issi.com rev. e 11/10/08 is24c01b is24c02b t able of contents features ..................3 description ....................3 f unctional block diagram .................4 pin confguration & description ..................5 device operations ...................6 absolute maximum ratings ..................14 dc characteristics ...................14 ac characteristics ...................15 ordering information ...................16 packaging information ....................17
integrated silicon solution, inc. www.issi.com 3 rev. e 11/10/08 is24c01b is24c02b 1k-bit/2k-bit 2-wire serial cmos eeprom description the is24c01b and is24c02b are eeprom de - vices that use the industrial standard 2-wire, i 2 c, interface for communications. the is24c01b and is24c02b contain a memory array of 1k-bits (128 x 8) and 2k-bits (256 x 8), respectively. each de - vice is organized into 8 byte pages for page write mode. this eeprom operates in a wide voltage range of 1.8v to 5.5v to be compatible with most applica - tion voltages. issi designed this device family to be a practical, low-power 2-wire eeprom solution. the devices are offered in lead-free, rohs, halo - gen free or green. the available package types are 8-pin soic, tssop, pdip, dfn, and csp. the is24c01b/02b maintains compatibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. the simple bus consists of the serial clock wire (scl) and the serial data wire (sda). using the bus, a master device such as a microcontroller is usually connected to one or more slave devices such as this device. the bit stream over the sda line includes a series of bytes, which identifes a particular slave device, an instruction, an address within that slave device, and a series of data, if ap - propriate. the is24c01b/02b has a write protect pin (wp) to allow blocking of any write instruction transmitted over the bus. f eatures ? two-wire serial interface, i 2 c tm compatible C bi-directional data transfer protocol ? wide voltage operation C vcc = 1.8v to 5.5v ? 400 khz (2.5v) and 1 mhz (5.0v) compatibility ? low power C standby current: 1 a or less (1.8v) C read current: 2 ma or less (5.0v) C write current: 3 ma or less (5.0v) ? hardware data protection C write protect pin ? sequential read feature ? filtered inputs for noise suppression ? self time write cycle with auto clear 5 ms max. @ 2.5v ? memory organization: C is24c01b: 128x8 (1k bits) C is24c02b: 256x8 (2k bits) ? 8-byte page write buffer ? high reliability C endurance: 1,000,000 cycles C data retention: 100 years ? industrial temperature grade ? packages: soic/sop, tssop, pdip, dfn, and csp copyright ? 2008 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equip - ment, aerospace systems, or for other applications planned to support or sustain life. it is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and prior placing orders for products.
4 integrated silicon solution, inc. www.issi.com rev. e 11/10/08 is24c01b is24c02b > control logic x decoder slave address register & comparator word address counter high voltage generator, timing & control eeprom array y decoder data register clock di/o ack 8 5 6 7 4 gnd wp scl sda vcc nmos 1 2 3 a2 a1 a0 functional block diagram
integrated silicon solution, inc. www.issi.com 5 rev. e 11/10/08 is24c01b is24c02b scl this input clock pin is used to synchronize the data transfer to and from the device. sda the sda is a bi-directional pin used to transfer addresses and data into and out of the device. the sda pin is an open drain output and can be wire-or'ed with other open drain or open collector outputs. the sda bus requires a pullup resistor to vcc. pin configuration 8-pin soic, tssop, pdip 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda pin descriptions a0-a2 address inputs sda serial address/data i/o scl serial clock input wp write protect input vcc power supply gnd ground a0, a1, a2 the a0, a1 and a2 are the device address inputs. the is24c01b/02b uses the a0, a1, and a2 for hardware addressing and a total of 8 devices may be used on a single bus system. when the a0, a1, or a2 inputs are left foating, the input internally defaults to zero. wp wp is the write protect pin. if the wp pin is tied to v c c on the eeprom, the entire array becomes write protected (read only). when wp is tied to gnd or left foating normal read/write operations are allowed to the device. 8-pad dfn 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda (top view)
6 integrated silicon solution, inc. www.issi.com rev. e 11/10/08 is24c01b is24c02b device operatio n is24c01b/02b features serial communication and supports a bi-directional 2-wire bus transmission protocol called i 2 c tm . 2-wire bus the two-wire bus is defned as a serial data line (sda), and a serial clock line (scl). the protocol defnes any device that sends data onto the sda bus as a transmitter, and the receiving devices as receivers. the bus is controlled by master device that generates the scl, controls the bus access, and generates the stop and start conditions. the is24c01b/02b is the slave device on the bus. the bus protocol: C data transfer may be initiated only when the bus is not busy C during a data transfer, the sda line must remain stable whenever the scl line is high. any changes in the sda line while the scl line is high will be interpreted as a start or stop condition. the state of the sda line represents valid data after a start condition. the sda line must be stable for the duration of the high period of the clock signal. the data on the sda line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. start condition the start condition precedes all commands to the device and is defned as a high to low transition of sda when scl is high. the eeprom monitors the sda and scl lines and will not respond until the start condition is met. stop condition the stop condition is defned as a low to high transition of sda when scl is high. all operations must end with a stop condition. acknowledge (ack) after a successful data transfer, each receiving device is required to generate an ack. the acknowledging device pulls down the sda line. reset the is24c01b/02b contains a reset function in case the 2-wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. the reset is caused when the master device creates a start condition. to do this, it may be necessary for the master device to monitor the sda line while cycling the scl up to nine times. (for each clock signal transition to high, the master checks for a high level on sda.) standby mode power consumption is reduced in standby mode. the is24c01b/02b will enter standby mode: a) at power-up, and remain in it until scl or sda toggles; b) following the stop signal if a no write operation is initiated; or c) following any internal write operation.
integrated silicon solution, inc. www.issi.com 7 rev. e 11/10/08 is24c01b is24c02b page write the is24c01b/02b is capable of 8-byte page-write operation. a page-write is initiated in the same manner as a byte write, but instead of terminating the internal write cycle after the frst data word is transferred, the master device can transmit up to 7 more bytes. after the receipt of each data word, the eeprom responds immediately with an ack on sda line, and the three lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. if a byte address is incremented from the last byte of a page, it returns to the frst byte of that page. if the master device should transmit more than 8 bytes prior to issuing the stop condition, the address counter will roll over, and the previously written data will be overwritten. once all 8 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the is24c01b/02b in a single write cycle. all inputs are disabled until completion of the internal write cycle. acknowledge (ack) polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the is24c01b/02b initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the eeprom is still busy with the write operation, no ack will be returned. if the is24c01b/02b has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write operatio n byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w set to zero) to the slave device. after the slave generates an ack, the master sends the byte address that is to be written into the address pointer of the is24c01b/02b. after receiving another ack from the slave, the master device transmits the data byte to be written into the address memory location. the is24c01b/02b acknowledges once more and the master generates the stop condition, at which time the device begins its internal programming cycle. while this internal cycle is in progress, the device will not respond to any request from the master device. device addressing the master begins a transmission by sending a start condition. the master then sends the address of the particular slave devices it is requesting. the slave device (fig. 5) address is 8 bits. the four most signifcant bits of the slave device address are fxed as 1010 for the is24c01b/02b. the next three bits of the slave address are specifc for each of the eeprom. the bit values enable access to multiple memory blocks or multiple devices. the is24c01b/02b uses the three bits a0, a1, and a2 in a comparison with the hard-wired input values on the a0, a1, and a2 pins. up to eight units may share the 2-wire bus. the last bit of the slave address specifes whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master transmits the start condition and slave address byte (fig. 5), the appropriate 2-wire slave (eg. is24c02b) will respond with ack on the sda line. the slave will pull down the sda on the ninth clock cycle, signaling that it received the eight bits of data. the selected eeprom then prepares for a read or write operation by monitoring the bus.
8 integrated silicon solution, inc. www.issi.com rev. e 11/10/08 is24c01b is24c02b read operation read operations are initiated in the same manner as write operations, except that the (r/ w ) bit of the slave address is set to 1. there are three read operation options: current address read, random address read and sequential read. current address read the is24c01b/02b contains an internal address counter which maintains the address of the last byte accessed, incremented by one. for example, if the previous operation is either a read or write operation addressed to the address location n, the internal address counter would increment to address location n+1. when the eeprom receives the slave addressing byte with a read operation (r/w bit set to 1), it will respond an ack and transmit the 8-bit data byte stored at address location n+1. the master should not acknowledge the transfer but should generate a stop condition so the is24c01b/02b discontinues transmission. if 'n' is the last byte of the memory, the data from location '0' will be transmitted. (refer to figure 8. current address read diagram.) random address read selective read operations allow the master device to select at random any memory location for a read operation. the master device frst performs a 'dummy' write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the is24c01b/02b acknowledges the byte address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the eeprom then responds with its ack and sends the data requested. the master device does not send an ack but will generate a stop condition. (refer to figure 9. random address read diagram.) sequential read sequential reads can be initiated as either a current address read or random address read. after the is24c01b/02b sends the initial byte sequence, the master device now responds with an ack, indicating it requires additional data from the is24c01b/02b. the eeprom continues to output data for each ack received. the master device terminates the sequential read operation by pulling sda high (no ack) indicating the last data word to be read, followed by a stop condition. the data output is sequential, with the data from address n followed by the data from address n+1,n+2 ... etc. the address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential read operation. when the memory address boundary of 127 or 255 (depending on the device) is reached, the address counter rolls over to address 0, and the device continues to output data. (refer to figure 10. sequential read diagram).
integrated silicon solution, inc. www.issi.com 9 rev. e 11/10/08 is24c01b is24c02b stop condition scl sda start condition figure 3. start and stop conditions scl sda master transmitter/ receiver is24cxx vcc figure 1. typical system b us conf iguration t aa data output from transmitter scl from master data output from receiver 18 9 ack t aa figure 2. output a ckn owledge
10 integrated silicon solution, inc. www.issi.com rev. e 11/10/08 is24c01b is24c02b figure 5. s lave address figure 4. d ata v alidity p rotocol scl sda data stable data stable data change figure 6. byte write sda bus activity s t a r t m s b l s b m s b w r i t e s t o p r/w a c k a c k a c k data device address byte address * 7 bit 4 3 1 2 5 6 0 r/w a0 a1 a2 0 1 0 1 * = don't care bit for is24c01b
integrated silicon solution, inc. www.issi.com 11 rev. e 11/10/08 is24c01b is24c02b figure 9. random address read sda bus activity a c k a c k a c k data n byte address (n) device address dummy write device address s t a r t w r i t e r e a d s t a r t s t o p m s b l s b n o a c k r/w * figure 7. p age w rite sda bus activity s t a r t m s b l s b w r i t e a c k a c k a c k a c k data (n+1) data (n) byte address (n) device address s t o p a c k data (n+7) r/w * figure 8. current address read sda bus activity s t a r t m s b l s b n o a c k r e a d s t o p a c k data device address r/w * = don't care bit for is24c01b * = don't care bit for is24c01b
12 integrated silicon solution, inc. www.issi.com rev. e 11/10/08 is24c01b is24c02b figure 10. seq uential read s t o p n o a c k a c k a c k a c k a c k data byte n+x data byte n+1 data byte n data byte n+2 r/w sda bus activity device address r e a d
integrated silicon solution, inc. www.issi.com 13 rev. e 11/10/08 is24c01b is24c02b ac wave forms f igure 11. bus timing t su:sta t f t high t low t r t su:sto t buf t dh t aa t hd:sta t hd:dat t su:dat scl sda in sda out t su:wp t hd:wp wp 8th bit ack word n stop condition start condition t wr scl sda f igure 12. write cycle timing
14 integrated silicon solution, inc. www.issi.com rev. e 11/10/08 is24c01b is24c02b dc electrical characteristics industrial (t a = -40 o c to +85 o c) symbol parameter test co nditions min. max. unit v o l 1 output low voltage v c c = 1.8v, i o l = 0.15 ma 0.2 v v o l 2 output low voltage v c c = 2.5v, i o l = 3 ma 0.4 v v i h input high voltage v c c x 0.7 v c c + 0.5 v v i l input low voltage C1.0 v c c x 0.3 v i l i input leakage current v i n = v c c max. 3 a i l o output leakage current 3 a notes: v i l min and v i h max are reference only and are not tested. power suppl y characteristics industrial (t a = -40 o c to +85 o c) symbol p arameter test cond itions min. max. unit i c c 1 operating current read at 400 khz (vcc = 5v) 2.0 ma i c c 2 operating current write at 400 khz (vcc = 5v) 3.0 ma i s b 1 standby current vcc = 1.8v 1 a i s b 2 standby current vcc = 2.5v 2 a i s b 3 standby current vcc = 5.0v 6 a absolute maximum rati ngs (1) symbol parameter value unit v s supply voltage C0.5 to +6.5 v v p voltage on any pin C0.5 to vcc + 0.5 v t b i a s temperature under bias C55 to +125 c t s t g storage temperature C65 to +150 c i o u t output current 5 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause per - manent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacita nce (1,2) symbol parameter conditions max. unit c i n input capacitance v i n = 0v 6 pf c o u t output capacitance v o u t = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c , f = 1 mhz, vcc = 5.0v.
integrated silicon solution, inc. www.issi.com 15 rev. e 11/10/08 is24c01b is24c02b ac electrical characteristics industrial (t a = -40 o c to +85 o c) 1.8v vcc < 2.5v 2.5v vcc < 4.5v 4.5v vcc 5.5v (1) symbol parameter (2) min. max. min. max. min. max. unit f s c l scl clock frequency 0 100 0 400 0 1000 khz t noise suppression time (1) 100 50 50 ns t l o w clock low period 4.7 1.2 0.6 s t h i g h clock high period 4 0.6 0.4 s t b u f bus free time before new transmission (1) 4.7 1.2 0.5 s t s u : s t a start condition setup time 4 0.6 0.25 s t s u : s t o stop condition setup time 4 0.6 0.25 s t h d : s t a start condition hold time 4 0.6 0.25 s t h d : s t o stop condition hold time 4 0.6 0.25 s t s u : d a t data in setup time 100 100 100 ns t h d : d a t data in hold time 0 0 0 ns t s u : w p wp pin setup time 4 0.6 0.6 s t h d : w p wp pin hold time 4.7 1.2 1.2 s t d h data out hold time 100 50 50 ns (scl low to sda data out change) t a a clock to output 100 3500 50 900 50 400 ns (scl low to sda data out valid) t r scl and sda rise time (1) 1000 300 300 ns t f scl and sda fall time (1) 300 300 100 ns t w r write cycle time 10 5 5 ms note: 1. this parameter is characterized but not 100% tested. 2. the timing is referenced to half vcc level.
16 integrated silicon solution, inc. www.issi.com rev. e 11/10/08 is24c01b is24c02b ordering inf ormation industrial range*: C40c to +85c voltage range part number* package type* (8-pin) 1.8v to 5.5v is24c01b-2gli 150-mil soic (jedec) IS24C01B-2ZLI 3 x 4.4 mm tssop is24c01b-2pli 300-mil pdip is24c01b-2cli csp 1.8v to 5.5v is24c02b-2gli 150-mil soic (jedec) is24c02b-2zli 3 x 4.4 mm tssop is24c02b-2pli 300-mil pdip is24c02b-2dli-tr 2 x 3 mm dfn is24c02b-2cli csp * 1. contact issi sales representatives for availability and other information. 2. most listed part numbers are packed in tube, except dfn. dfn is only offered in -tr. 3. for tape and reel, add -tr at the end of the p/n. 4. refer to issi website for related declaration document on lead free, rohs, halogen free, or green, whichever is applicable. 5. issi offers industrial grade for commercial applications (0 o c to +70 o c).
integrated silicon solution, inc. www.issi.com 17 rev. e 11/10/08 is24c01b is24c02b
18 integrated silicon solution, inc. www.issi.com rev. e 11/10/08 is24c01b is24c02b thin shrink small outline tssop package code: z (8 pin, 14 pin) rev b 02/01/02 tssop (z) ref. std. jedec mo-153 no. leads 8 millimeters inches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 d 2.90 3.10 0.114 0.122 e1 4.30 4.50 0.169 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 ?8 ?8 tssop (z) ref. std. jedec mo-153 no. leads 14 millimeters inches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.10 0.193 0.201 e1 4.30 4.50 0.170 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.0177 0.0295 ?8 ? 8 d b e e1 a2 e c a a1 l 1 n n/2
integrated silicon solution, inc. www.issi.com 19 rev. e 11/10/08 is24c01b is24c02b 300-mil plastic dip package code: n,p a d 1 b n seating plane c a1 e a l e b1 s e1 e s for 32-pin only b2 millimeters inches sym. min. max. min. max. n0. leads 8 a 3.68 4.57 0.145 0.180 a1 0.38 ? 0.015 ? b 0.36 0.56 0.014 0.022 b1 1.14 1.52 0.045 0.060 b2 0.81 1.17 0.032 0.046 c 0.20 0.33 0.008 0.013 d 9.12 9.53 0.359 0.375 e 7.62 8.26 0.300 0.325 e1 6.20 6.60 0.244 0.260 e a 8.13 9.65 0.320 0.380 e 2.54 bsc 0.100 bsc l 3.18 ? 0.125 ? s 0.64 0.762 0.025 0.030 notes: 1. controlling dimension: inches, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be measured from the bottom of the package . 4. formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
20 integrated silicon solution, inc. www.issi.com rev. e 11/10/08 is24c01b is24c02b dual flat no-lead package code: d (8-pad) a2 a2 b (8x) (8x) a1 a3 a3 d e a l (8x) l (8x) e (6x) e (6x) 1.50 ref. 1.50 ref. d2 d2 e2 pad 1 id pad 1 index area tie bars (3) notes: 1. refer to jedec drawing mo-229. 2. this is the metallized terminal and is measured between 0.18 mm and 0.30 mm from the terminal tip. the terminal may have a straight end instead of rounded. 3. package may have exposed tie bars, ending flush with package edge. dfn millimeters sym. min. nom. max. n0. pad 8 d 2.00 bsc e 3.00 bsc d2 1.50 ? 1.75 e2 1.60 ? 1.90 a 0.70 0.75 0.80 a1 0.0 0.02 0.05 a2 ? ? 0.75 a3 0.20 ref l 0.30 0.40 0.50 e 0.50 bsc b 0.18 0.25 0.30

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